Scientists from EPFL’s Integrated Systems Laboratory (LSI) have developed a new type of logic diagram for optimizing electronic circuits.
This could be used to design new-age computer chips that offer nearly 20% gain in energy efficiency, speed or size.
According to the scientists, using a different set of logic functions for the gates on the billions of transistors on electronic circuits, could help shorten the circuits’ calculation steps.
This could enable chip designers to make their chips either smaller, faster or more energy efficient.
Synopsys, a global leader in electronic design automation and chip fabrication software, has just acquired the rights to use EPFL’s technology through a non-exclusive license agreement.
Today most engineers use electronic design automation software to design circuits.
This software programs translate complex computational models into a labyrinth of billions of microscopic transistors.
Hoping to simplify this, former LSI laboratory scientist Luca Amarù set out to radically change how design automation software generates logic diagrams in order to produce better designs.
Amarù came up with a method that uses only two logic primitives: majority and inverter. These functions are displayed in majority-inverter graphs (MIGs).
Initial studies indicated that his approach could cut the number of logic steps needed to execute a given task.
Later experiments confirmed this, finding that MIG optimization reduces the number of logic levels by 18% on average relative to standard programs.
That frees up transistor capacity for other tasks; engineers could also use these gains to make their chips faster or their devices smaller.
Amarù, now a senior R&D manager at Synopsys, further developed a new Boolean algebra for representing the logic functions, resulting in additional efficiency gains for his system.
Lab tests have shown that Amarù’s method also works exceptionally well with components already in the market, such as adders and dividers.
Image and content: Analogicus-Pixabay/EPFL